| Reference | Claim Element / Subject Matter | Feature | Meaning | Claim Construction & Interpretation |
|---|---|---|---|---|
| [1] |
1 . A method [1] |
method [1] |
[Meaning 1] process [Meaning 2] technique [Meaning 3] system [Meaning 4] scheme [Meaning 5] control method [Meaning 6] memory method [Meaning 7] dynamic method [Meaning 8] method of [Meaning 9] computer implemented method [Meaning 10] data processing method [Meaning 11] power management method [Meaning 12] method and apparatus [Meaning 13] semiconductor memory method [Meaning 14] non transitory transitory method |
[Interpretation 1] circuit for reducing power consumption during background operations in an array with at least two sections comprising the steps of claims claims 1a method [Interpretation 2] memory array with at least one plurality of sections according to claim 10 or claim 11 [Interpretation 3] memory device comprising at least one memory array with at least one section method [Interpretation 4] power management method for memory arrays with sections of different power consumption [Interpretation 5] semiconductor memory device comprising at least one processor and memory controller [Interpretation 6] program and computer readable storage medium for carrying out the method [Interpretation 7] power management method for memory arrays with multiple sections and methods |
| [2] | for reducing (reducing the amount of, improving the efficiency of, providing an optimization of, reducing the area required and, providing an efficient reduction in, controlling the time and the, enabling and disabling low voltage) power consumption [2] | power consumption [2] |
[Meaning 1] power [Meaning 2] latency [Meaning 3] noise [Meaning 4] current [Meaning 5] interference [Meaning 6] current consumption [Meaning 7] energy consumption [Meaning 8] noise generated [Meaning 9] data loss [Meaning 10] memory access time [Meaning 11] power consumption occurring [Meaning 12] or eliminating power consumption [Meaning 13] the number of cycles [Meaning 14] power consumption and noise |
[Interpretation 1] the power consumption of an integrated circuit memory device with an array of peripheral circuits in which the power consumption is reduced [Interpretation 2] the power consumption of an integrated circuit memory device in response to one or more control signals and an address signal [Interpretation 3] the number of address lines required to enable the operation of peripheral array circuits in one or more memory sections [Interpretation 4] power consumption in an integrated circuit memory device in which at least one memory cell is accessed [Interpretation 5] power consumption in an integrated circuit memory device by reducing the number of active row lines [Interpretation 6] access time in an integrated circuit memory device by reducing the number of access cycles occurring [Interpretation 7] current consumption in an integrated circuit memory device in which the current consumption is reduced only [Interpretation 8] noise in an integrated circuit memory device in which noise is generated by memory cells [Interpretation 9] access time to memory cells in one or more of said sections [Interpretation 10] the number of power down cycles in one or more peripheral circuits [Interpretation 11] current consumption in memory arrays with multi section memory cells |
| [3] | during background operations [3] | background operations [3] |
[Meaning 1] background [Meaning 2] operations [Meaning 3] standby [Meaning 4] memory operations [Meaning 5] foreground operations [Meaning 6] performing background operations [Meaning 7] background operations performed [Meaning 8] background operations of memory cells [Meaning 9] operation of at least one background [Meaning 10] background operations of an access operation [Meaning 11] non volatile memory background operations carried out [Meaning 12] read and write background operations of an address signal |
[Interpretation 1] background operations in an integrated circuit memory device with an array of sections comprising the steps of reducing power consumption during said background operations [Interpretation 2] memory access in an integrated circuit with at least one periphery array circuit of at least one periphery array for controlling background operations performed [Interpretation 3] read and write operations in memory arrays with sections of the same size and shape comprising the steps of controlling background operations performed [Interpretation 4] memory access in an integrated circuit memory device in which background operations are performed on data stored [Interpretation 5] the background operations of an integrated circuit memory device having at least one memory cell [Interpretation 6] non volatile memory access operations in the presence of background operations performed [Interpretation 7] read and write background operations of one or more cells [Interpretation 8] the background operations of one or more memory cells contained |
| [4] | in a memory array [4] | memory array [4] |
[Meaning 1] memory [Meaning 2] dram [Meaning 3] device [Meaning 4] circuit [Meaning 5] array [Meaning 6] semiconductor memory [Meaning 7] storage array [Meaning 8] dram array [Meaning 9] flash memory array [Meaning 10] dynamic memory array [Meaning 11] memory array provided [Meaning 12] dynamic random access memory [Meaning 13] multi section memory array [Meaning 14] program addressable memory array |
|
| [5] | with a plurality of sections [5] | sections [5] |
[Meaning 1] section [Meaning 2] portions [Meaning 3] areas [Meaning 4] compartments [Meaning 5] memory sections [Meaning 6] sections therein [Meaning 7] sectioned sections [Meaning 8] section circuits [Meaning 9] addressable sections therein [Meaning 10] separate sections and [Meaning 11] sections of memory cells [Meaning 12] memories sections said method [Meaning 13] sections of said memory array [Meaning 14] memory sections and peripheral circuits |
[Interpretation 1] memory cells and at least one periphery array circuit for controlling said plurality of memory cells and having at least two or more sections [Interpretation 2] rows and columns and at least one periphery array circuit with at least one plurality of sections of memory cells [Interpretation 3] rows and columns and at least one plurality of sections of said memory array in said memory array [Interpretation 4] memory cells arranged in at least two or more sections of said memory array said method further [Interpretation 5] sections of said memory array in communication with each other and said method [Interpretation 6] sections of memory cells and associated peripheral array circuits and |
| [6] | comprising (wherein said method comprises, of memory cells comprising, said method characterized by, comprising the method comprising, of said memory array comprising, arranged in an array comprising, in which the method comprises) the steps of : controlling (selectively enabling and disabling, enabling one or more, controlling the enablement of, disabling at least one of, controlling the power consumption during) said background operations [3] in each of said plurality of sections [5] of said memory array [4] in response [6] | response [6] |
[Meaning 1] accordance [Meaning 2] relation [Meaning 3] responsive [Meaning 4] correspondence [Meaning 5] direct response [Meaning 6] turn according [Meaning 7] turn in response [Meaning 8] parallel in response [Meaning 9] an independent response [Meaning 10] an independent manner according [Meaning 11] independent manner in response [Meaning 12] said memory in response [Meaning 13] accordance with and in response [Meaning 14] said plurality of sections in response |
[Interpretation 1] the presence of one or more decode said address signals and one or more decode said address signals are generated in response in response [Interpretation 2] the presence of one or more decode output address signals and said background operations are enabled in response [Interpretation 3] the absence of said background operations in any other section of said memory array in response [Interpretation 4] accordance with one or more decode signal generated by said plurality of sections in response [Interpretation 5] accordance with one or more background operations control signals in response [Interpretation 6] said memory array with one or more circuits in response [Interpretation 7] the absence of said power consumption reduction method in response |
| [7] | to one or more control signals [7] | control signals [7] |
[Meaning 1] signals [Meaning 2] control [Meaning 3] commands [Meaning 4] controls signals [Meaning 5] command signals [Meaning 6] signal controls [Meaning 7] respective control signals [Meaning 8] program selectable control signals [Meaning 9] control signals generated therein [Meaning 10] control signals in said sections [Meaning 11] of said plurality of sections [Meaning 12] decode and decode address signals [Meaning 13] of one or more control signals [Meaning 14] controls signals in said memory array |
[Interpretation 1] control signals and one or more decode said address signals generated by one or more control logic circuits of said plurality of memory sections [Interpretation 2] of one or more control signals and one or more decode address signals generated in response to an address signal [Interpretation 3] of one or more control signals and one or more decode address signals presented to said plurality of sections [Interpretation 4] signals generated by one or more control logic circuits in said memory array for controlling background operations [Interpretation 5] signals generated in response to one or more decode address signals respectively [Interpretation 6] decode address signals and one or more decode address control signals [Interpretation 7] signals generated in response to one or more program control signals |
| [8] | , wherein said one or more control signals [7] are generated (at least partially generated, one or more signals, provided to said sections, stored in said sections, generated by said controller, stored in said memory array, one or more bits generated) in response [6] to a programmable address signal [8] | address signal [8] |
[Meaning 1] signal [Meaning 2] parameter [Meaning 3] address [Meaning 4] code [Meaning 5] value [Meaning 6] control signal [Meaning 7] mode signal [Meaning 8] logic signal [Meaning 9] bit pattern [Meaning 10] background control signal [Meaning 11] mode of operation signal [Meaning 12] power reduction mode signal [Meaning 13] bit of said address [Meaning 14] control signal generator circuit |
[Interpretation 1] logic device in said memory array and one or more decode address signals generated in response to said one or more control signals and [Interpretation 2] logic device in said memory array and decode the address signals of said plurality of sections respectively [Interpretation 3] logic device in said memory array and said one or more control signals are independent [Interpretation 4] logic device program to control said background operations in said plurality of sections [Interpretation 5] bit of an address signal presented to said memory array [Interpretation 6] logic device in said memory array and said background operations |
| [9] | and said background operations [3] can be enabled (carried out independently or, initiated and carried out, performed in parallel or, simultaneously or non 20, carried out in parallel or, either performed sequentially or performed, performed in any section or) simultaneously in two or more of said plurality of sections [5] independently of any other section [9] | section [9] |
[Meaning 1] sections [Meaning 2] operation [Meaning 3] mode [Meaning 4] background operations [Meaning 5] control signals [Meaning 6] said section [Meaning 7] memory section [Meaning 8] enabled section [Meaning 9] plurality of sections [Meaning 10] section or sections [Meaning 11] sections of said plurality [Meaning 12] sections of said memory array [Meaning 13] background operations in said memory array [Meaning 14] of said one or more control signals |
[Interpretation 1] control signals in said plurality of sections and independently of any other address signals in said memory array [Interpretation 2] control signals in response to one or more decode signals of said program address signal [Interpretation 3] background operations in said two or more of said plurality of sections simultaneously [Interpretation 4] sections of said plurality of sections and any other background operations [Interpretation 5] one or more of said plurality of sections being enabled |
| [10] | ; and presenting (selectively providing one of, generating signals corresponding to, providing in response to, transmitting in parallel both, providing at least one of, generating and transmitting one of, generating one or more signals comprising) said one or more control signals [7] and one or more decoded (of said program selectable, other said program program, decode and program enable, non program program memory, of said one or more, addresses corresponding to said program selectable) address signals [10] | address signals [10] |
[Meaning 1] signals [Meaning 2] addresses [Meaning 3] data [Meaning 4] bits [Meaning 5] outputs [Meaning 6] command signals [Meaning 7] data signals [Meaning 8] control signals [Meaning 9] output signals [Meaning 10] column address signals [Meaning 11] address signals simultaneously [Meaning 12] program selectable address signals [Meaning 13] bits of said address [Meaning 14] address signals in parallel |
[Interpretation 1] address signals to one or more peripheral array circuits of said memory array to reduce power consumption during said background operations presented [Interpretation 2] output signals to one or more peripheral array circuits of said plurality of sections to reduce the power consumption presented [Interpretation 3] output signals from said plurality of sections to one or more peripheral array circuits to reduce power consumption [Interpretation 4] control signals generated in response to said program selectable address signal [Interpretation 5] output signals of said one or more program selectable address signals |
| [11] | to one or more periphery array circuits [11] | periphery array circuits [11] |
[Meaning 1] sections [Meaning 2] others [Meaning 3] outputs [Meaning 4] drivers [Meaning 5] selected sections [Meaning 6] other sections [Meaning 7] of each [Meaning 8] decoder circuits [Meaning 9] corresponding sections [Meaning 10] drivers in each [Meaning 11] columns in each [Meaning 12] circuits in each [Meaning 13] of said sections [Meaning 14] sections of each |
[Interpretation 1] decoder circuits for decoding said program selectable address signal in each [Interpretation 2] decode logic circuits for decoding said program signal to enable one |
| [12] | of said plurality of sections [5] . |